1. Field of the Invention
This invention relates generally to power amplifier circuits, and more particularly to an ultra low voltage CMOS, class AB power amplifier that uses inherent parasitic capacitance to accomplish internal compensation.
2. Description of the Prior Art
Numerous techniques are known for achieving class AB amplifiers with quiescent current control. These conventional techniques generally employ an input gain stage in front of a class AB output stage, and use well-known Miller capacitance techniques to compensate for the input gain stage in order to achieve the requisite amplifier stability.
One common technique to achieve stability for a class AB output stage uses a source-follower stage in parallel with the primary output MOSFET in order to provide a feed-forward zero and thereby assist the desired stability (compensation). Due to circuit complexity and component matching characteristics, these designs are not optimal.
In CMOS power amplifiers, the input gate capacitance, C.sub.gs, has been problematic due to its relatively large value (caused by its very large output device gate area). As requirements for driving lower and lower speaker impedance (32.OMEGA..fwdarw.4), and a reduced power supply environment (2.7V.fwdarw.1.5V), makes the output power FETs grow larger and larger, their parasitic capacitance, C.sub.gs, continues to grow. Recent developments in CMOS technology continue to grow this trend.
In view of the foregoing, a need exists for a CMOS power amplifier that has high drive capability in combination with lower quiescent current drain and more efficient use of available supply voltage than currently available using conventional CMOS class AB power amplifiers.